CD Datasheet, CD PDF, CD Data sheet, CD manual, CD pdf, CD, datenblatt, Electronics CD, alldatasheet, free, datasheet. CD Datasheet, CD PDF. Datasheet search engine for Electronic Components and Semiconductors. CD data sheet, alldatasheet, free, databook. Data sheet acquired from Harris Semiconductor. SCHS Page 2. Page 3. Page 4. Page 5. IMPORTANT NOTICE. Texas Instruments and its subsidiaries (TI ).
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These systems may be either special or general purpose in nature. It is written for electronics engineers and assumes only a limited familiarity with computers and computer programming. It describes the microprocessor architecture and provides a set of simple, easy-to-use programming instructions. Examples are given to illustrate the operation and usage of each instruction.
For systems designers, this Manual illustrates practical methods of adding external memory and control circuits. The latter include direct-memory -access and interrupt inputs, external flag inputs, command lines, processor state indica- tors, and external timing pulses.
This Manual also discusses various programming techniques and gives examples. The material covers, dataeheet addition to basic guidelines, more advanced topics such datashee interrupt response and subroutine link- age and nesting. This basic Manual is intended to help design engineers understand the COSMAC Microprocessor and to aid them in developing simpler and more powerful products utilizing the wide range of microproces- sor capabilities.
Users requiring information on available hardware and software support systems for the CDP Microprocessor should also refer to the following publications: These applications range from replacement of SSI and MSI integrated circuits to new applications requiring the full flexibility of a computer-based approach.
CDP operations are specified by sequences of instruction codes stored in a memory. Sys- tt ‘unctions are easily changed by modifying the pro- giu This ability to change function without extensive hardware modification is the basic advantage of a stored-program computer. Reduced cost results from using identical LSI components memory and microprocessor in a variety of different systems or products.
The CDP Microprocessor includes all of the cir- cuits required for fetching, interpreting, and executing instructions which datsheet been stored in standard types of memories. Although Microprocessor cost is only a small part of total system or product cost memory, input, output, power-supply, system-control, and design costs are also major considerationsa unique set of COSMAC features combine to minimize the total system cost.
For exam- ple, the low-power, single-voltage CMOS circuitry mini- mizes power-supply and packaging costs. A single-phase clock drives the system and an optional on-chip oscilla- tor circuit works with an external crystal to provide this clock signal.
Datasehet noise immunity and wide cc4076 tolerance facilitate use in hostile environments. In addi- tion, compatibility with standard, high-volume memories assures minimum memory cost and maximum system flexibility for both current and future applications. Pro- gram storage requirements are reduced by means of an efficient one-byte operation code.
Microprocessor programming and system design are facilitated by the availability of a variety of support pro- grams and support hardware. Machine-language programming is sometimes indicated when only a few short programs need to be developed. A series of efficient, easy -to-learn instructions are provided for the CDP which are simple to use in machine-language programs. Operations that can be performed include: In such a system, the CDP can, for example, control the entry of binary -coded decimal numbers from an input keyboard and store them in predetermined memory locations.
It can then perform specified arith- metic operations using the vd4076 numbers and transfer the results to an output display or printing device. ROM Read- Only Memory is used for permanent storage of pro- grams, tables, and other types of fixed data. RAM Random-Access Memory is required for general- purpose computer systems which require frequent pro- gram changes. RAM is also required for temporary storage of variable data. The type of memory and re- quired storage capacity is determined by the specific application of the system.
These flags can also be used as binary input lines if desired. They can be tested by CDP instructions to determine whether or not they are active. Use of the flag inputs must be coordinated with pro- grams that test them. The interrupt causes the CDP to suspend its current program sequence and execute a predeter- mined sequence of operations designed to respond to the interrupt condition.
These lines are called direct-memory-access DMA lines. Activating the DMA-in line causes an input byte to be immediately stored in a memory location without inter- vention by the program being executed. The DMA-out line causes a byte to be immediately transferred from memory to the requesting output circuits. A built-in memory pointer register is used to indicate the memory location for the DMA cycles.
The program initially sets this pointer to a beginning memory location. Each DMA “e transfer automatically increments the pointer to. Repeated activation of a DMA line can cause the transfer of any number of con- secutive bytes to and from memory independent of con- current program execution.
The flag lines must be sampled by the program to determine when they become active and are used for relatively slow changing signals. Activating the interrupt line causes an immediate COSMAC response regardless of the program currently in progress, suspending operation of that pro- gram and allowing real-time response.
Use of DMA pro- vides the quickest cx4076 with least disturbance of the program. The state code indicates whether the CDP1S02 is responding to a DMA request, responding to an interrupt request, fetching datasheeh instruc- tion, or ‘executing an instruction.
Bytes are transmitted to and from memory by means of the common data bus. The CDP provides eight memory address lines. These eight lines supply bit memory addresses in the form of two successive 8-bit bytes. The more significant high-order address byte appears on the eight address lines first, followed by the less significant low-order address byte.
The number of high-order bits required to select a unique memory byte location depends on the size of the memory. For example, a cf4076 memory would require a bit address.
This bit address is ob- tained by combining 4 bits from the high-order address byte with the 8 bits from the low-order address byte.
DATASHEETS CD40xx, CD41xxxx, CD42xx, CD43xx, CD44xx, CD45xx, CD47xx
One of the two CDP timing pulses may be used to strobe the required high-order bits into an address latch register when they appear on the eight address lines. Latch circuits are not required at all if address registers are incorporated on the memory chips, as in the RCA series ROM’s. An internal CPU register datasyeet the eight low-order address bits on the eatasheet lines for the remainder of the memory cycle.
Four additional lines complete the microprocessor system interface. A single-phase clock input determines operating speed. The external clock may be stopped and started to synchronize the CDP operation with system circuits if desired. C onstru ction of the clock circuit is simplified by use of XTAL input. A crystal is connected between XTAL and clock input; no active components are needed. The clear input line initializes the microprocessor, and its release starts instruction exe- cution.
The wait line suspends the CPU operation clean- ly. Simultaneous assertion of clear and wait puts the CPU in a program load mode.
This simple, unique architecture results in a number of vd4076 advantages. Each datashedt register, R, is designated by a 4-bit binary code. Hexadecimal hex notation will be used here to refer to 4-bit binary codes. The 16 hexa- decimal digits 0,1,2, Using hex notation, R 3 refers to the bit scratch- pad register designated or selected by the binary code Three 4-bit registers labeled N, P, and X hold the 4-bit binary codes hex digits that are used to select individual bit scratch-pad registers.
The 16 dafasheet con- tained in a selected scratch-pad can be used in several ways. Either byte can also be gated to the 8-bit data bus for subsequent transfer to the D register. The bit value in the A register can also be incremented datzsheet decremented by 1 and returned to the selected scratch-pad register to permit a scratch- pad register to be used as a counter.
The designated scratch-pad register is left unchanged. The right half of Fig. The following sequence of steps is required to perform datasehet operation: O is gated to the bus. Daasheet cycles involve both an address and the data byte itself. Memory addresses are provided by the con- tents of scratch-pad registers. The following steps are required: Reading a byte from memory does not change the con- tents of memory.
The 8-bit arithmetic-logic unit ALU in Fig. The byte stored in the D register is one operand, and the byte on the bus left side of Cd476. The re- sultant byte replaces the operand in D. A single-bit register data flag DF is set to “0” if no carry results from an add or shift operation. DF is fatasheet to “1” if a carry does occur. The 8-bit D register is similar to the accumulator found in many computers.
The internal flip-flop Q can be set or reset by instruc- tions, and can be sensed by conditional branch instruc- tions. The state of Q is also available as a microprocessor output.
A one-byte instruction format is applicable for most instructions. Two 4-bit hex digits contained in each instruction byte are designated as I and N, as shown in Fig. For most instructions, the execution requires two machine cycles. The First cycle fetches or reads the appropriate instruction byte from memory and stores the two hex instruction digits in registers I and N. The values in I and N specify the operation to be performed during the second machine cycle.
I specifies the instruc- tion type. Depending upon the c4076, N either designates a scratch-pad register, as illustrated in Fig.